In the application of quartz crystal resonators and ceramic resonators, attention should be paid to the choice of load capacitance. The characteristics and quality of quartz crystal resonators and ceramic resonators produced by different manufacturers are quite different. When selecting, it is necessary to understand the key indicators of this type of oscillator, such as equivalent resistance, manufacturer recommended load capacitance, frequency deviation and so on. In the actual circuit, the oscillating waveform can also be observed by an oscilloscope to determine whether the oscillator is operating at its optimum state. When observing the oscillating waveform, the oscilloscope observes the OSCO pin (Oscillator output). It should select an oscilloscope probe with a bandwidth of 100MHz or more. This probe has high input impedance, small capacitive reactance, and relatively little influence on the oscillating waveform. (Because there is usually 10~20pF of capacitance on the probe, it is better to reduce the capacitance on the OSCO pin to obtain a more realistic oscillation waveform when observing). A well-functioning oscillating waveform should be a beautiful sine wave with a peak-to-peak value greater than 70% of the supply voltage. If the peak-to-peak value is less than 70%, the external load capacitance on the OSCI and OSCO pins can be appropriately reduced. Conversely, if the peak-to-peak value is close to the power supply voltage and the oscillation waveform is distorted, the load capacitance can be appropriately increased. Using an oscilloscope to detect the OSCI (Oscillatorinput) pin can easily cause the oscillator to stop vibrating due to:
Part of the probe impedance is not directly testable, and can be tested by string capacitor method. For example, a commonly used 4MHz quartz crystal resonator, the external load capacitance recommended by the manufacturer is usually about 10~30pF. If the center value is 15pF, then C1 and C2 each take 30pF to obtain a series equivalent capacitance of 15pF. At the same time, considering the additional distributed capacitance of the board, the chip pin capacitance, the crystal's own parasitic capacitance, etc. will affect the total capacitance value. Therefore, when C1 and C2 are actually configured, each can take about 20~15pF, and C1 and C2 use porcelain. The chip capacitor is better.
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